Dr. Mayur Agarwal
Department : Electronics and Communication Engineering
Email-id: agrmayur@gmail.com
Qualification: Ph.D
Designation: Assistant Professor (TEQIP-III)
Research Interests: VLSI Design
Publications:
1. J. Kandpal, A. Tomar, M. Agarwal and K. K. Sharma, “High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell,†in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, pp. 1413-1422, June 2020, doi: 10.1109/TVLSI.2020.2983850.
2. M. Agarwal, A. De and S. Banerjee, “An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System,†in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 6, pp. 2275-2287, June 2019, doi: 10.1109/TCSI.2019.2892459.
3. J. Kandpal, A. Tomar, K. Pandey and M. Agarwal, “High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology,†2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE), Dehradun Uttarakhand, India, 2019, pp. 192-195, doi: 10.1109/WITCONECE48374.2019.9092897.
4. M. Agarwal, A. Mishra and S. Banerjee, “VLSI architecture for IEEE single precision floating point moving average calculator,†in 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, 2017, pp. 1-4, doi: 10.1109/IPACT.2017.8244978.
5. M. Agarwal, A. De and S. Banerjee, “Architecture of a real-time delay calculator for digital beamforming in ultrasound system,†in IET Circuits, Devices & Systems, vol. 10, no. 4, pp. 322-329, 7 2016, doi: 10.1049/iet-cds.2015.0189.
6. M. Agarwal, N. Agrawal and M. A. Alam, “A new design of low power high speed hybrid CMOS full adder,†2014 International Conference on Signal Processing and Integrated Networks (SPIN), Noida, 2014, pp. 448-452, doi: 10.1109/SPIN.2014.6776995.
FDP Attended:
1. 2 Week course on Digital Transformation in Teaching Learning Process
2. Advanced Pedagogy on Digital Tools in Indian Institute of Technology, Delhi
FDP Organised:
1. Latest Trends in VLSI Design and hands-on Implementation using EDA tools
Projects:
1. Project Title: A Hardware-Efficient Beamformer for Portable, Low Cost Ultrasound Imaging System
Starting Date: 2019-07-01
Duration: 01 Years 06 Months
Status: Ongoing
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